软件说明
- Scalable across FPGA technology, quick adoption of newest FPGA
- Supports scalable hardware platforms with backplane or extension slots
- Scalable for increasing design sizes with incremental and parallel synthesis and implementation
- Supports scalable simulation acceleration and emulation clusters
- Reuse the same hardware across different teams: simulation, emulation, prototyping
Top Features: Supported Boards
- Off the shelf FPGA boards HES-7 by Aldec
- In-house made custom boards (with Xilinx FPGA: Virtex-5, Virtex-6, Virtex-7)
Verification Interfaces
- Simulation acceleration (various simulators: Active-HDL, Riviera-PRO, third party simulators)
- SystemVerilog DPI-C for transaction level and UVM simulation acceleration
- PLI/VHPI for bit-level acceleration
- SCE-MI and TLM for transaction level co-emulation
- Easy integration with C/C++, SystemC, Verilog, SystemVerilog, and VHDL
- Supported on Linux and MS Windows
Automated Design Setup
- Complete design setup toolset – DVM
- Design compilation front-end supporting latest standards of SystemVerilog and VHDL
- Behavioral compiler for transactors supporting SV DPI-C and Implicit State Machines (ISM)
- Incremental design synthesis with 3rd party synthesis tools
- Self-constrained and automated implementation with FPGA vendor tools (Xilinx Vivado, ISE)
- Automatic and guided partitioning
- Automatic gated clock conversion with unlimited number of clock domains
- Memory flow to map design memories to board or FPGA resources
- Debugging aware design processing with automatic code instrumentation
- Parallel computing with LSF and SGE and design setup scalability
- TCL scripting and GUI available
Debugging Capabilities
- HVD technology for 100% visibility with reduced number of captured probes
- Configurable triggering
- Hardware breakpoints
- Clocks control (Stop, Run, Step)
- Saving debug data in waveform files: ASDB for Riviera-PRO and FSDB for Verdi
- Memory back-door access for read & write
- HW Debugger tool with GUI to manage debug process also remotely via LAN.
- C/C++ HES Debug API